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Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators

Publication Type:

Conference/Workshop Paper

Venue:

28th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems


Abstract

Deploying deep learning models on resource constrained hardware like Field-Programmable Gate Arrays (FPGAs) remains challenging despite advancements in quantization techniques, which often fail to map optimally to target hardware. This study proposes an end-to-end workflow for fixed-point quantization targeting FPGA accelerators, integrating hardware emulation within quantization-aware training to bridge software-hardware co-design. This ensures quantized models are optimized for real-world deployment. Evaluations on CIFAR-10 and ImageNet datasets using ResNet and VGG models show competitive performance, with up to 2% improvement in accuracy over state-of-the-art methods. This work provides insights to resolve the discrepancies that often occur between software based quantization and hardware deployment. Our methodology effectively bridges quantization and deployment, providing a practical solution for edge device applications.

Bibtex

@inproceedings{Mogaka7190,
author = {Obed Mogaka and H{\aa}kan Forsberg and Masoud Daneshtalab},
title = {Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators},
month = {May},
year = {2025},
booktitle = {28th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems},
url = {http://www.es.mdu.se/publications/7190-}
}