{"id":1211,"date":"2023-01-18T08:28:46","date_gmt":"2023-01-18T07:28:46","guid":{"rendered":"https:\/\/www.es.mdh.se\/hero\/?page_id=1211"},"modified":"2023-01-18T11:48:15","modified_gmt":"2023-01-18T10:48:15","slug":"coma","status":"publish","type":"page","link":"https:\/\/www.es.mdu.se\/deephero\/coma\/","title":{"rendered":"CoMA"},"content":{"rendered":"\t\t
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CoMA: Configurable Many-core Accelerator for Embedded Systems<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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On early embedded systems, accelerators were placed on a separate chip next to the main processor, or on an independent board connected to the main system. Nowadays, it is common to find systems where a general purpose processors (e.g. ARM and ATOM) and several accelerators are integrated on the same chip (e.g. XILINX ZYNQ). The high level of complexity of these circuits has been reflected on their non-recurring engineering and manufacturing cost. As a consequence, many-core embedded systems are mainly mass-produced in the form Application Specific Integrated Circuits (ASICs) for covering the needs of large markets. Two negative effects are derived from this. first is, medium and small size companies which cannot afford manufacturing their own chips are unable to provide customized solutions even if they possess the necessary know-how. This leads to non-optimal implementations based on the chips available on the market. Second and most important, is the lack of many-core architectures for highly specialized markets. The design space exploration for these systems is hampered by low production volumes since they do not justify the costs of developing an ASIC. One possible alternative for fulfilling this gap is the utilization of field-programmable Gate Arrays (FPGAs). In [1][2][3], we have developed a Configurable Many-core Accelerator (CoMA) for FPGA-based embedded systems. Its architecture comprises an array of processing and I\/O-specialized cores interconnected by a Network-on-Chip (NoC) [4]. The I\/O cores provide the connectivity with other system components through the industry-standard Advanced eXtensible Interface (AXI) bus. In a typical design flow, an application is partitioned and the most compute-demanding tasks are executed on the accelerator. With the proposed approach, the details of task synchronization and I\/O access of the accelerator are hidden by an abstraction layer. Task partitioning is left to the designer, thus allowing more flexibility during application development than with automatized partitioning. The high level view of the system leverages the customization of the accelerator on an application basis. This way, CoMA promotes the development of many-core solutions for highly specialized applications.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Fig. 1. CoMA Architecture.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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The architecture combines an array of processing cores interconnected by an NoC, with an I\/O interface based on the AXI protocol. CoMA provides the designer with a system abstraction layer that facilitates task partitioning and peripheral access. The implementation of the I\/O interface was verified through simulation, and synthesized for an FPGA.

The key features of CoMA are as following:<\/p>