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Model Based Development of Embedded Systems using Logical Clock Constraints and Timed Automata


PhD defense

Start time:

2013-12-09 13:15

End time:

2013-12-09 17:15


room Kappa, Mälardalen University, Västerås

Contact person:



  • Professor Robert de Simone; INRIA Sophia Antipolis - Méditerranée research centre.

Grading Committee:

  • Martin Törngren, Professor, KTH Royal Institute of Technology; 
  • Peter Czaba Ölveczky, Professor, University of Oslo; 
  • Elena A. Troubitsyna, Associated Professor, Åbo Akademi University.


  • Paul Pettersson, Professor, MDH 
  • Cristina Seceleanu, Sr. Lecturer, MDH.


In modern times, human life is intrinsically depending on real-time embedded systems (RTES) with increasingly safety-critical and mission-critical features, for instance, in domains such as automotive and avionics. These systems are characterized by stringent functional requirements and require predictable timing behavior. However, the complexity of RTES has been ever increasing requiring systematic development methods. To address these concerns, model-based frameworks and component-based design methodologies have emerged as a feasible solution. Further, system artifacts, such as requirements, architectural designs as well as behavioral models like statemachine views, are integrated within the development process. However, several challenges remain to be addressed, out of which two are especially important: expressiveness, to represent the real-time and causality behavior, and analyzability, to support verification of functional and timing behavior. As the main research contribution, this thesis presents design and verification techniques for model-based development of RTES, addressing expressiveness and analyzability for architectural and behavioral models. To begin with, we have proposed a systematic design process to support component based development. Next, we have provided a real-time semantic basis, in order to support expressiveness and verification for structural and behavioral models. This is achieved by defining an intuitive formal semantics for real-time component models, using ProCom, a component model developed at our research centre, and also using CCSL (Clock Constraint Specification Language), an expressive language for specification of timed causality behavior. This paves the way for formal verification of both architectural and behavioral models, using model checking, as we show in this work, by transforming the models into timed automata and performing verification using UPPAAL, a model checking tool for timed automata. Finally, the research contributions are validated using representative examples of RTES as well as an industrial case-study.

Jagadish Suryadevara,