You are required to read and agree to the below before accessing a full-text version of an article in the IDE article repository.
The full-text document you are about to access is subject to national and international copyright laws. In most cases (but not necessarily all) the consequence is that personal use is allowed given that the copyright owner is duly acknowledged and respected. All other use (typically) require an explicit permission (often in writing) by the copyright owner.
For the reports in this repository we specifically note that
- the use of articles under IEEE copyright is governed by the IEEE copyright policy (available at http://www.ieee.org/web/publications/rights/copyrightpolicy.html)
- the use of articles under ACM copyright is governed by the ACM copyright policy (available at http://www.acm.org/pubs/copyright_policy/)
- technical reports and other articles issued by M‰lardalen University is free for personal use. For other use, the explicit consent of the authors is required
- in other cases, please contact the copyright owner for detailed information
By accepting I agree to acknowledge and respect the rights of the copyright owner of the document I am about to access.
If you are in doubt, feel free to contact webmaster@ide.mdh.se
Data Caches in Multitasking Hard Real-Time Systems
Publication Type:
Conference/Workshop Paper
Venue:
International Real-Time Systems Symposium (RTSS)
Abstract
Data caches are essential in modern processors, bridging the
widening gap between main memory and processor speeds. However,
they yield very complex performance models, which makes it hard to
bound execution times tightly.This paper contributes a new technique to obtain predictability in
preemptive multitasking systems in the presence of data caches. We
explore the use of cache partitioning, dynamic cache
locking and it static cache analysis to provide worst-case
performance estimates in a safe and tight way. Cache partitioning
divides the cache among tasks to eliminate inter-task cache
interferences. We combine static cache analysis and cache locking
mechanisms to ensure that all intra-task conflicts, and
consequently, memory access times, are exactly predictable. To
minimize the performance degradation due to cache partitioning and
locking, two strategies are employed. First, the cache is loaded
with data likely to be accessed so that their cache utilization is
maximized. Second, compiler optimizations such as tiling and
padding are applied in order to reduce cache replacement misses.Experimental results show that this scheme is fully predictable,
without compromising the performance of the transformed programs.
Our method outperforms static cache locking for all analyzed task
sets under various cache architectures, with a CPU utilization
reduction ranging between 3.8 and 20.0 times for a high
performance system.
Bibtex
@inproceedings{Vera499,
author = {Xavier Vera and Bj{\"o}rn Lisper and Jingling Xue},
title = {Data Caches in Multitasking Hard Real-Time Systems},
month = {December},
year = {2003},
booktitle = {International Real-Time Systems Symposium (RTSS)},
publisher = {IEEE},
url = {http://www.es.mdu.se/publications/499-}
}