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Design and Analysis of Charge-Pump Based Frequency Synthesizers
Publication Type:
Licentiate Thesis
Publisher:
Mälardalen University Press
Abstract
Most telecommunication systems employ modulation techniques that
require the transceiver to be capable of accurately estimating the
phase of the transmission signal. The frequency synthesizer is a
key element and extensively utilized to synthesize frequencies for
such radio-frequency communication systems. A common topology for
the frequency synthesizer is the charge-pump based phase-locked
loop. The development and design of frequency synthesizer is known
to be a complex and time-consuming task, aggravated by the vast
difference in frequencies between the output and the internal
signals. It is often necessary to perform long transient
simulations with short time steps to achieve reliable results.
This thesis will treat these difficulties and propose solutions to
some of the design issues that concerns the frequency synthesizer.In most modern frequency synthesizers the phase detection circuits
are capable of detecting both the frequency and phase difference.
Such phase detectors are collectively known as phase-frequency
detectors and generally employ some kind of memory functionality.
The inherited memory in the phase-frequency detectors rouse the
need for new models describing the synthesizer. Throughout this
thesis the dynamic and noise behavior in the presence of
phase-frequency detector are especially investigated. The derived
theory and conclusions are validated through earlier presented
research as well as simulations of both the phase-frequency
detector and the frequency synthesizer.A high reference frequency is often sought after in frequency
synthesizers, since it then becomes possible to lower the division
ratio in the frequency synthesizer. This will in turn lower the
close-in phase noise of the synthesizer as well as decrease the
power consumption of the divider chain. Unfortunately, it has also
been shown that the size of the phase-frequency detectors
blind-zone is directly proportional to the reference input
frequency. Consequently, frequency synthesizers, utilizing high
reference frequencies, will also have to include the effects of
the phase-frequency detector's blind zone to accurately estimate
the frequency synthesizer behavior. The blind-zone effect will
become even more important as the tendency for high reference
frequencies is further pursued. This thesis, therefore,
investigates the influence of the phase-frequency detector blind
zone. The results from these investigations have shown that a
large blind zone is deteriorative for the settling time, but has
little influence on the synthesizer noise performance. However,
for an exceptional large blind zone there is the possibility that
noise, present in the circuit, will force the synthesizer out of
the locked condition.Nonlinear models are developed and utilized to fully capture the
frequency synthesizer's dynamic behavior both in the locked and
out-of-locked condition. The models are presented in the
state-space form to facilitate simulations and to describe the
internal variables within the synthesizer. Two different closed
formulas for the settling time are given for a synthesizer with
and without a phase-frequency detector exhibiting blind zone.For the phase noise performance in the frequency synthesizer the
nonlinear state-space model has been expanded with time-domain
noise sources correlated according to the input noise sources. The
linearized phase-domain noise model is compared to the state-space
model. The comparison shows that the phase-domain model describes
the phase noise property of the synthesizer well below the loops
bandwidth. However, for offsets larger than the loop bandwidth the
linearized phase-domain is insufficient.
Bibtex
@misc{Johnson748,
author = {Tord Johnson},
title = {Design and Analysis of Charge-Pump Based Frequency Synthesizers},
number = {46},
month = {April},
year = {2005},
publisher = {M{\"a}lardalen University Press},
url = {http://www.es.mdu.se/publications/748-}
}