TIMERS - Timing analysis, modeling and evaluation of RTS



Start date:


In this project, we address various issues related to the synthesis, modeling, analysis and implementation of embedded systems in `real` industrial settings. This project can be described as the second phase of the DOORS project, since many of the industrial issues addressed here has arisen out of problems faced and our experiences during that project. The project includes:
  • Architecture design and analysis, that is, how is an architecture for an embedded system designed and analyzed with respect to both functional and non-functional properties.
  • Definition of new architecture description languages with a precise syntax and semantics to enable both analysis and synthesis to a resource structure.
  • Mapping of architecture to a resource structure, especially we are studying an unified approach to priority assignment for fixed priority systems.
  • Development of new scheduling algorithms, which could provide `optimal` performance in terms of control performance (rather than just feasibility). Another objective is to provide sufficient motivation for the industry and help them to select the `right` scheduling paradigm suitable to the application domain and task timing characteristics.
  • Fault modeling and studies on the effects of errors on timing analysis
  • Development of tools, which supports analysis as well as synthesis to resource structures.

Christer Norström,

Email: christer.norstrom@sics.se
Room: U3-133
Phone: +46-21-101464