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Verifying MARTE/CCSL Mode Behaviors using UPPAAL


Publication Type:

Conference/Workshop Paper


11th International Conference on Software Engineering and Formal Methods


In the development of safety-critical embedded systems, the ability to formally analyze system behavior models, based on timing and causality, helps the designer to get insight into the system’s overall timing behavior. To support the design and analysis of real-time embedded systems, the UML modeling profile MARTE provides CCSL – a time model and a clock constraint specification language. On the one hand, CCSL is an expressive language that supports specification of both logical and chronometric constraints associated with MARTE models. On the other hand, semantic frameworks such as Timed Automata provide verification support for real-time systems. To tackle the challenge of verifying CCSL-based system properties, in this paper, we propose a technique for transforming MARTE/CCSL mode behaviors into Timed Automata for model-checking using the UPPAAL tool. This enables verification of both logical and chronometric properties of the system, which has not been possible before. We demonstrate the proposed transformation and verification approach using two relevant examples of real-time embedded systems.


author = {Jagadish Suryadevara and Cristina Seceleanu and Frederic Mallet and Paul Pettersson},
title = {Verifying MARTE/CCSL Mode Behaviors using UPPAAL},
month = {September},
year = {2013},
booktitle = {11th International Conference on Software Engineering and Formal Methods},
url = {}