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Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures - A technical report
Publication Type:
Report - MRTC
Publisher:
Mälardalen Real-Time Research Centre, Mälardalen University
ISRN:
MDH-MRTC-293/2014-1-SE
Abstract
Dynamic RAM (DRAM) is a source of memory contention and interference
problems on COTS multicore architectures. Due to its variable access time, it
can greatly influence the task’s WCET and can lead to unpredictability. In this
paper, we provide a worst case delay analysis for a DRAM memory request to
safely bound memory contention on multicore architectures. We derive a worstcase
service time for a single memory request and then combine it with the perrequest
memory interference that can be generated by the tasks executing on same
or different cores in order to generate the delay bound.
Bibtex
@techreport{Inam3725,
author = {Rafia Inam and Moris Behnam and Mikael Sj{\"o}din},
title = {Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures - A technical report},
month = {October},
year = {2014},
publisher = {M{\"a}lardalen Real-Time Research Centre, M{\"a}lardalen University},
url = {http://www.es.mdu.se/publications/3725-}
}