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Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures


Publication Type:

Conference/Workshop Paper


Seventh Swedish Workshop on Multicore Computing


Dynamic RAM (DRAM) is a source of memory contention and interference problems on commercial of the shelf (COTS) multicore architectures. Due to its variable access time, it can greatly influence the task's WCET and can lead to unpredictability. In this paper, we provide a worst case delay analysis for a DRAM memory request to safely bound memory contention on multicore architectures. We derive a worst-case service time for a single memory request and then combine it with the per-request memory interference that can be generated by the tasks executing on same or different cores in order to generate the delay bound.


author = {Rafia Inam and Moris Behnam and Mikael Sj{\"o}din},
title = {Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures},
month = {November},
year = {2014},
booktitle = {Seventh Swedish Workshop on Multicore Computing},
url = {}