Xavier Vera (not working at IDT anymore)

Xavi is a PhD student at CSLab. He obtained his M.Sc degree in Computer Science at Universitat Politecnica de Catalunya (UPC) in Spain (2000), and got the Licentiate degree in March 2002 at IDT/MDH. His current research focuses on high level cache behavior for embedded systems. Other topics: cache compiler optimizations and clustered architecures.

Main Supervisor: Björn Lisper Advisor: Jingling Xue Advisor: Jan Gustafsson

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Latest publications:

Data cache locking for tight timing calculations (Dec 2007)
Xavier Vera, Björn Lisper, Jingling Xue
ACM Transactions on Embedded Computing Systems

An accurate cost model for guiding data locality transformations (Sep 2005)
Xavier Vera, Jaume Abella , Josep Llosa , Antonio Gonzalez
ACM Trans. Program. Lang. Syst.

A Fast and Accurate Framework to Analyze and Optimize Cache Memory Behavior (Mar 2004)
Xavier Vera, Nerina Bermudo , Josep Llosa , Antonio Gonzalez
ACM Transactions on Programming Languages and Systems (TOPLAS)

Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior (Jan 2004)
Jingling Xue , Xavier Vera
To appear in IEEE Transactions on Computers

Cache and Compiler Interaction (how to analyze, optimize and time cache behavior) (Jan 2004)
Xavier Vera

Data Caches in Multitasking Hard Real-Time Systems (Dec 2003)
Xavier Vera, Björn Lisper, Jingling Xue
International Real-Time Systems Symposium (RTSS)