SARA - Scaleable Architecture for RT Applications



SARA is a project being executed, by a group working at the Department of Computer Engineering at Mälardalens University, the Computer Architecture Laboratory (CAL).

The project is based on a previous project sponsored by the KK-foundation, industry and the university. The project has evaluated an accelerator (the Real-Time Unit; RTU) for single processor real-time operating systems and designed multiprocessor real-time systems. The research project started in 1989 at Erlangen (Germany) with a single person and the group has now 11 persons. In recent years the group has worked with hardware design methodology and with successful industrial projects.

The lifecycle for real-time (embedded) applications is becoming shorter, the application complexity increases, performance is too low, fault tolerance is required, reuse of components is desired and the developer requires strong verification tools to speed up the verification phase. As the problem increases in terms of longer development times and higher quality requirements from the customer, it becomes increasingly important to develop flexible and scalable parallel processing for complex real-time systems. This is the main motivation for the research project.

The SARA ApproachThe new approach is defined by the following design goals:
  • Efficiency,
  • Performance and
  • Flexibility.
High performance is one of the most important goals in a multi-processor system. To achieve a high performance the system must be based on state-of-the-art, commercial, standard microprocessors, busses, and different hardware accelerators etc. Unfortunately, caches, pipelines, etc yield predictability problems. Deterministic high performance processor architectures are possible to develop, but it is difficult to compete with the big processor companies.
An architecture for Processor Scalability is a flexible way to increase the performance for the application. The architecture should be a scaleable open system with no theoretical limit. A node can consist of hundreds of processors and can be hierarchically structured. The system can be configured as a mix of loose and hard-coupled system. There is a need for an \