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Evaluation of Delay Queues for a Ravenscar Hardware Kernel
Publication Type:
Report - MRTC
ISRN:
MDH-MRTC-176/2005-1-SE
Abstract
In this paper we present and evaluate four delay queues designed for
application tailored Ravenscar hardware real-time kernels. The
properties of the different queues and optimisations of them are
discussed and both formal models and actual hardware implementation of
the queues are presented. A transformation from timed automata to VHDL
is described during the translation of the timed automata of the
formal model into the corresponding VHDL state machines. Our study of
the queues shows that even though parallelism costs much in terms of
chip area, there are system configurations where it is the most space
conservative. We also show that the queues meet the timing
requirements of Ravenscar and that they can be fitted onto an FPGA.
Bibtex
@techreport{Naeser711,
author = {Gustaf Naeser and Johan Furun{\"a}s-{\AA}kesson},
title = {Evaluation of Delay Queues for a Ravenscar Hardware Kernel},
number = {ISSN 1404-3041 ISRN MDH-MRTC-176/2005-1-SE},
month = {April},
year = {2005},
url = {http://www.es.mdu.se/publications/711-}
}