The need for high-performance computing is increasing at a daunting pace and computational heterogeneity is the answer. High-performance computing platforms are increasingly becoming heterogeneous, meaning that they contain a combination of different computational units such as CPUs, GPUs, FPGAs, and AI accelerators. This computational power is needed both in hyped products like autonomous vehicles, but also in (maybe) less obvious cases like industrial automation where future intelligent production will be based on smart, autonomous, and collaborative industrial robots.
When this diverse range of computing architectures are put together on a single board (or a single chip even); the main challenge is to maximize the use of the huge computational power and at the same time to meet several criteria like performance, energy efficiency, real-time response, and dependability. To overcome these challenges, programmers of heterogeneous systems are expected to write parallel software, explicitly describe potential parallelism in their code, and identify which computations should be executed by which type of computational units. Currently, these activities are mostly manual, thereby difficult, slow, and error-prone.
The overall goal of HERO is to provide a framework that enables development of optimized parallel software, automatic mapping of software to heterogeneous hardware platforms, and provision of automatic hardware acceleration for the developed software.
Through HERO, Mälardalen University and five companies will develop deep competence to bridge the syntactic and semantic gap between modeling and programming languages, as well as automatically manipulating artifacts for analysis and synthesis of software for multiple heterogeneous targets. We will be able to drastically enhance the current practices for the design, analysis, and synthesis of parallel software for heterogeneous platforms. We will advance the knowledge on how to design and implement efficient functions for next-generation advanced hardware platforms and develop support for hardware programming, thanks to automatic synthesis of accelerators for heterogeneous parallel platforms.
HERO represents a substantial step towards an innovative solution for systematic and efficient development of complex heterogeneous systems. The research conducted in HERO is expected to provide substantial advances to the current state of the art in (i) model-based development and resource analysis of parallel software, (ii) pre-runtime code-level resource analysis, and (iii) automatic hardware acceleration.
The HERO team is composed of a strong group of researchers covering all aspects of the Synergy, with proven research records, and a group of companies strategically important for Swedish industry. Moreover, the Embedded Systems research environment at Mälardalen University represents the ideal soil for HERO, where we draw from, and contribute, to the rich and deep competence in embedded systems.
|Associate Professor,Docent,Head of Research Education
|Associated Senior Lecturer
Pattern-Based Verification of ROS 2 Nodes using UPPAAL (Sep 2023) Lukas Dust, Rong Gu, Cristina Seceleanu, Mikael Ekström, Saad Mubeen FMICS 2023 - International Conference on Formal Methods for Industrial Critical Systems (FMICS 2023)
Comparative Evaluation of Various Generations of Controller Area Network Based on Timing Analysis (Sep 2023) Aldin Berisa, Mohammad Ashjaei, Masoud Daneshtalab, Mikael Sjödin, Adis Panjevic , Imran Kovac , Hans Lyngbäck , Saad Mubeen 28th International Conference on Emerging Technologies and Factory Automation (ETFA 2023)
Experimental Evaluation of Callback Behavior in ROS 2 Executors (Sep 2023) Lukas Dust, Emil Persson, Mikael Ekström, Saad Mubeen, Cristina Seceleanu, Rong Gu 28th International Conference on Emerging Technologies and Factory Automation (ETFA 2023)
Investigating and Analyzing CAN-to-TSN Gateway Forwarding Techniques (May 2023) Aldin Berisa, Mohammad Ashjaei, Masoud Daneshtalab, Mikael Sjödin, Saad Mubeen 2023 IEEE 25th International Symposium on Real Time Distributed Computing (ISORC) (ISORC'23)
NeuroPIM: Flexible Neural Accelerator for Processing-in-Memory Architectures (May 2023) Ali Monavari , Sepideh Fattahi , Mehdi Modarressi , Masoud Daneshtalab International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)